Espressif’s ESP32-S31: RISC-V Power Play or Branding Blunder?

In the fiercely competitive world of microcontrollers, Espressif has just lobbed a curveball that’s turning heads - and raising eyebrows. The newly unveiled ESP32-S31 MCU promises impressive technical upgrades, but its unexpected architecture swap is leaving even seasoned developers scratching their heads. Is this a bold step into the future, or a branding misfire destined to muddy the waters?

Fast Facts

• ESP32-S31 features dual-core RISC-V CPUs running up to 320 MHz.
• Supports WiFi 6, Bluetooth Classic, Bluetooth LE 5.4 (including LE Audio), Thread, and Zigbee.
• Upgrades Ethernet to gigabit speeds, departing from previous 100 Mbit limits.
• Boasts 60 GPIO pins - 15 more than the ESP32-S3.
• Currently available only as samples to select customers; general release date unannounced.

The Architecture Anomaly

Traditionally, Espressif’s ESP32-S series has relied on Tensilica’s Xtensa LX7 cores, while the C-series was reserved for RISC-V architectures. The S31 breaks this convention, introducing dual RISC-V cores into the S-series for the first time. For those who’ve built IoT projects around Espressif’s predictable naming, it’s a jarring shift. The RISC-V cores - clocked up to 320 MHz - promise performance on par with, or even exceeding, the previous LX7-based S3 models, thanks to improvements in instructions per cycle (IPC).

But this isn’t just a CPU swap. The ESP32-S31 brings a raft of upgrades: WiFi 6 for faster, more efficient wireless connections; Bluetooth Classic and LE 5.4 with support for new audio standards; and, for the first time, gigabit Ethernet, a major leap from the 100 Mbit MAC found in earlier chips. Add in support for Thread and Zigbee, and this chip is clearly aimed at the next wave of connected devices.

Hardware hackers will also appreciate the expanded set of GPIO pins - now 60, up from 45 - opening up new possibilities for complex designs. Memory handling gets a boost too, with DDR PSRAM supported via fast octal SPI (up to 250 MHz), compared to the S3’s 80 MHz limit.

Confusion in the Ranks

Yet, the decision to brand a RISC-V chip under the S-series umbrella has sown confusion. Is this a sign that Espressif is phasing out Xtensa cores, or simply testing the waters? The company has been tight-lipped about availability, with only select customers getting early samples. For now, the ESP32-S31 stands as both a technical milestone and a branding puzzle - one that could signal a broader shift in Espressif’s product strategy.

Looking Ahead

As the line between Espressif’s product families blurs, developers and tinkerers are left to wonder: is this the dawn of a unified RISC-V future, or just a confusing detour? Either way, the ESP32-S31 is poised to shake up the microcontroller landscape - once it finally hits the market.

WIKICROOK

• RISC: RISC is a processor design using a reduced set of instructions, enabling faster execution and efficiency in devices like smartphones and servers.
• WiFi 6: WiFi 6 is the latest wireless standard, offering faster speeds, better efficiency, and improved performance in crowded areas with many connected devices.
• GPIO: GPIO are configurable pins on hardware boards used for input or output, enabling direct control and communication with external devices.
• PSRAM: PSRAM is a memory chip that expands RAM in embedded devices, offering DRAM-like density with easy SRAM-like interfacing for efficient memory management.
• Thread: Thread is a wireless protocol for smart homes, allowing devices to communicate directly in a secure, reliable mesh network without cloud dependency.